#Adlock 2020 software
41-45, 2015.This software is only about removing ads but also provide safe browsing, spyware, anti-tracking, and malware services. Kahng et al., "ORION3.0: A comprehensive NoC router estimation tool," IEEE Embedded Systems Letters, vol. Binkert et al., "The Gem5 simulator," ACM SIGARCH Computer Architecture News, vol. Princeton University Princeton, NJ, 2011.
#Adlock 2020 serial
Pasricha, "Exploring serial vertical interconnects for 3D ICs," in DAC, 2009. Catania et al., "Cycle-accurate network on chip simulation with noxim," ACM TOMACS, vol. Taheri et al., "Adele: An adaptive congestion-and-energy-aware elevator selection for partially connected 3D NoCs," in DAC, 2021. Hsiao et al., "Electromigration reliability and morphologies of Cu pillar with microbump under high current density stressing," in EPTC, 2015. Li et al., 3D microelectronic packaging: From fundamentals to applications. Salamat et al., "A resilient routing algorithm with formal reliability analysis for partially connected 3D-NoCs," IEEE TC, vol.
Ebrahimi et al., "Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy," in DATE, 2013. Pasricha et al., "A low overhead fault tolerant routing scheme for 3D networks-on-chip," in ISQED, 2011. Bharadwaj et al., "Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling," in DAC, 2020. Glass et al., "The turn model for adaptive routing," ACM SIGARCH Computer Architecture News, vol. Majumder et al., "Remote control: A simple deadlock avoidance scheme for modular systems-on-chip," IEEE TC, 2020. Yin et al., "Modular routing design for chiplet-based systems," in ISCA, 2018. Wang et al., "Pre-bond testing of the silicon interposer in 2.5D ICs," in DATE, 2016.
#Adlock 2020 verification
Ebrahimi et al., "EbDa: A new theory on design and verification of deadlock-free interconnection networks," in ISCA, 2017. Ma et al., "TAP-2.5D: A thermally-aware chiplet placement methodology for 2.5D systems," in DATE, 2021. Kim et al., "Architecture, chip, and package co-design flow for 2.5D IC design enabling heterogeneous IP reuse," in DAC, 2019. Taheri et al., "Addressing a new class of reliability threats in 3-D network-on-chips," IEEE TCAD, vol. Kannan et al., "Enabling interposer-based disintegration of multi-core processors," in MICRO, 2015. Compared to the state-of-the-art routing algorithms in 2.5D chiplet systems, our simulation results show that DeFT improves network reachability by up to 75% with a fault rate of up to 25% and reduces the network latency by up to 40% for multi-application execution scenarios with less than 2% area overhead. Moreover, DeFT can tolerate different vertical-link-fault scenarios while accounting for vertical-link utilization. DeFT improves the redundancy in vertical-link selection to tolerate faults in vertical links while considering network congestion. To address these problems, this paper presents the first deadlock-free and fault-tolerant routing algorithm, called DeFT, for 2.5D integrated chiplet systems. Unfortunately, existing fault-tolerant routing techniques proposed for 2D and 3D on-chip networks cannot be applied to chiplet networks.
Nevertheless, the underlying network is prone to deadlock, despite deadlock-free chiplets, and to different faults on the vertical links used for connecting the chiplets to the interposer. By interconnecting smaller chiplets through an interposer, 2.5D integration offers a cost-effective and high-yield solution to implement large-scale modular systems.
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